Logic Synthesis for FSM-Based Control Units by Alexander Barkalov (English) Pape

Description: Logic Synthesis for FSM-Based Control Units by Alexander Barkalov, Larysa Titarenko This book presents the hardware implementation of control algorithms represented by graph-schemes of algorithm. It includes new methods of logic synthesis and optimization for logic circuits of Mealy and Moore FSMs oriented on both ASIC and FPLD. FORMAT Paperback LANGUAGE English CONDITION Brand New Publisher Description Tremendous achievements in the area of semiconductor electronics turn - croelectronics into nanoelectronics. Actually, we observe a real technical boom connected with achievements in nanoelectronics. It results in devel- mentofverycomplexintegratedcircuits,particularlythe?eldprogrammable logic devices (FPLD). Up-to-day FPLD chips are so huge, that it is enough only one chip to implement a really complex digital system including a da- path and a control unit. Because of the extreme complexity of modern - crochips, it is very important to develop e?ective design methods oriented on particular properties of logic elements. The development of digital s- tems with use of FPLD microchips is not possible without use of di?erent hardware description languages(HDL), such as VHDL and Verilog. Di?erent computer-aided design tools (CAD) are wide used to develop digital system hardware. As majorityof researchespoint out, the design processis nowvery similar to the process of program development. It allows a researcher to pay more attention to some speci?c problems, where there are no standard f- mal methods of their solution.But application of all these achievements does not guaranteeper sedevelopmentof some competitiveelectronic product,- pecially in the acceptable time-to-market. This problem solution is possible only if a researcher possesses fundamental knowledge of a design process and knows exactly the mode of operation of industrial CAD tools in use. As it is known, any digital system can be represented as a composition of a da- path and a control unit. Back Cover The control unit is one of the most important parts of any digital system responsible for interplay of other system blocks. Very often, the model of a finite state machine (FSM) is used to represent the behaviour of a control unit. Modern computer-aided design tools include a lot of optimal solutions (library cells) for implementation of such regular blocks of digital systems as decoders, multiplexers, parallel multibit adders and so on. But as a rule, control units have an irregular structure which makes impossible to design their logic circuits using the standard library cells. To use these cells, an FSM can be represented by a multilevel model based on the principle of structural decomposition. In multilevel models, for example, multiplexers are used to replace logical conditions, decoders are used to implement microoperations, and different memory blocks are used to transform object codes. Design methods depend strongly on such factors as an FSM model in use, specific features of logic elements implementing its logic circuit, characteristics of a control algorithm to be interpreted. In the case of Moore FSM, optimization methods are based on existence of the classes of pseudoequivalent states. Their use permits to compress the transition table of Moore FSM till the size of the table for equivalent Mealy FSM. In the case of Mealy FSM, optimization methods are based on transformation of either object codes, or interpreted graph-schemes of algorithm. In the case of CPLD, the hardware decrease can be achieved using more than single source of state codes. In the case of FPGA, the structural decomposition allows using embedded memory blocks for implementation of decoding logic. In case of ASIC, design methods target on minimization of the chip area occupied by an FSM circuit. It can be achieved due to use of different encoding methods, where both internal states and collections of microoperations can be encoded. If a control algorithm is a linear one, then a state register of Moore FSM can be replaced by a counter. It leads to simplification of the input memory functions and, in turns, to the hardware amount decrease. The book includes a lot of design methods targeted on logic synthesis of both Mealy and Moore FSMs, where their logic circuits can be implemented using ASIC, as well as CPLD or FPGA. The most of discussed methods belong to the authors of this book. This book will be interesting and useful for students and postgraduates in the area of Computer Science, as well as for designers of digital systems included complex control units. Proposed models and design methods open new possibilities for creating logic circuits of control units with optimal hardware amount. Table of Contents Hardwired Interpretation of Control Algorithms.- Matrix Realization of Control Units.- Evolution of Programmable Logic.- Optimization for Logic Circuit of Mealy FSM.- Optimization for Logic Circuit of Moore FSM.- FSM Synthesis with Transformation of GSA.- FSM Synthesis with Object Code Transformation.- FSM Synthesis with Elementary Chains.- Conclusion. Long Description Tremendous achievements in the area of semiconductor electronics turn - croelectronics into nanoelectronics. Actually, we observe a real technical boom connected with achievements in nanoelectronics. It results in devel- mentofverycomplexintegratedcircuits,particularlytheeldprogrammable logic devices (FPLD). Up-to-day FPLD chips are so huge, that it is enough only one chip to implement a really complex digital system including a da- path and a control unit. Because of the extreme complexity of modern - crochips, it is very important to develop eective design methods oriented on particular properties of logic elements. The development of digital s- tems with use of FPLD microchips is not possible without use of dierent hardware description languages(HDL), such as VHDL and Verilog. Dierent computer-aided design tools (CAD) are wide used to develop digital system hardware. As majorityof researchespoint out, the design processis nowvery similar to the process of program development. It allows a researcher to pay more attention to some specic problems, where there are no standard f- mal methods of their solution. But application of all these achievements does not guaranteeper sedevelopmentof some competitiveelectronic product,- pecially in the acceptable time-to-market. This problem solution is possible only if a researcher possesses fundamental knowledge of a design process and knows exactly the mode of operation of industrial CAD tools in use. As it is known, any digital system can be represented as a composition of a da- path and a control unit. Feature Presents the hardware implementation of control algorithms represented by graph-schemes of algorithm Useful for students, practitioners, and researchers in electrical engineering and digital automata design Includes new methods of logic synthesis and optimization for logic circuits of Mealy and Moore FSMs oriented on both ASIC and FPLD, as well as a lot of examples Details ISBN3642260640 Author Larysa Titarenko Publisher Springer-Verlag Berlin and Heidelberg GmbH & Co. KG Series Lecture Notes in Electrical Engineering Year 2012 ISBN-10 3642260640 ISBN-13 9783642260643 Format Paperback Imprint Springer-Verlag Berlin and Heidelberg GmbH & Co. K Place of Publication Berlin Country of Publication Germany Short Title LOGIC SYNTHESIS FOR FSM-BASED Language English Media Book Series Number 53 Pages 233 Edition 2010th Publication Date 2012-03-14 Edition Description 2010 ed. Alternative 9783642043086 DEWEY 621.3981 Audience Professional & Vocational Illustrations XIX, 233 p. We've got this At The Nile, if you're looking for it, we've got it. With fast shipping, low prices, friendly service and well over a million items - you're bound to find what you want, at a price you'll love! TheNile_Item_ID:96265825;

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